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Lectures
Lecture 30 Template
30 -
Outline
Memory Access Time
Multi-Level Page Tables
Recap
Recap:
Effective Access Time
Announcements
Reading:
Page Replacement
Alternative Approaches
Memory Access Time
Multilevel Page Tables
1)
3)
4)
2)
MOS 3.3 - 3.7
Quiz Friday
Virtual Memory
0xdeadb
...
...
0xb
frame 0xb
f
...
...
0xeef
o
page table
TLB
physical
memory
virtual address
physical address
0xbeef
TLB is a specialized cache for page table entries.
Define:
then
Comparison and loading is faster on hit.
Miss causes page table access and TLB update.
-
-
:= TLB lookup time
is negligible (TLB lookup is very fast)
is close to 1 (TLB misses very rare)
:= RAM access time
:= hit ratio (fraction of TLB hits)
:= effective access time
Assuming:
In practice, TLB can be designed so that misses
are rare under most conditions, and the cost of
misses is negligble.
Page table size grows exponentially with number of
address bits.
Multilevel Page Table --> page the page table
Only portions of a page table need to be kept in
RAM (rest don't exist or on disk)
Downside: worst case, misses require 3+ accesses
Fortunately TLB can be designed for high hit rate
Larger TLB increases hit ratio
TLB hardware architecture affects hit ratio
-
-
fully associative, set associative, direct-mapped caches...
e.g. 64-bit address, 4kB page => 2^52 pages
split page number bits into primary and
secondary page number
drastically reduce required memory
primary page table
secondary page table
data
-
-
-
-
-
primary
secondary
...
f
...
offset
o
secondary
page tables
primary
page table
physical
memory
virtual address
physical address
...
32-bit virtual address space.
4kB page.
4B page table entry.
Application requires 12MB of RAM.
Same size primary and secondary page table.
What if there are 5 bits for the primary table, and
15 bits for the secondary page?
Note: typically the page table sizes are the same
for hardware cost reasons.
Index table by frame number instead of page
number.
What is the minimum RAM needed to store all the
page tables the application needs?
Exercise
Inverted Page Table (Frame Table)
Hashed Page Table
PollEv
Modern processors can use up to 4 or 5 levels of
page tables
(e.g. Intel Ice Lake & ARMv7-A)
Hints:
how big are the primary and secondary page
tables?
how many total page tables are needed to
access 12MB's worth of RAM?
-
-
1k
1M
1G
1T
1P
1E
= 2^10
= 2^20
= 2^30
= 2^40
= 2^50
= 2^60
Alternative Approaches
Page Replacement
table size proportional to RAM size
(much smaller than virtual address space)
translation requires linear search for page num
much slower
TLB can help, but worst case is still terrible
-
-
-
-
0xdeadb
...
...
0xdeadb
frame 0xb
f
...
...
0xeef
o
frame table
TLB
physical
memory
virtual address
physical address
0xbeef
0xb
linear
search
0xb
Hash the page number to index into a linked list
linked list necessary for hash collisions
must store both page and frame number
-
-
0xdeadb
...
f
...
0xeef
o
page table
physical
memory
virtual address
physical address
hash
function
3
p
f
p
p
f
f
p
f
p
f
process
OS
disk
...
...
free frame
...
...
page table
main memory
i
(1)
(6)
(2)
(3)
(4)
(5)
What happens when there is no free frame?
Need some algorithm for determining which page to
replace with the one from disk.
Page Replacement Algorithms
Goal:
Evaluation format:
Algorithms
Demand Paging & Prepaging
Related:
Working Set Model
Page Allocation
Thrashing
Optimal
Not Recently Used
2nd Chance
Not Frequently Used
Clock
Aging
First In, First Out
Least Recently Used
Example:
reference string:
In:
Out:
select a victim page that will minimize
future page faults
a string of memory references.
(i.e. list of accessed pages)
number of page faults the algorithm causes
for that string.
replacing a page that will be needed again soon will cause
more page faults
str r0, 0x0123
str r1, 0x1234
str r2, 0x2345
str r3, 0x3456
ld r0, 0x0100
ld r1, 0x1200
str r4, 0x4567
page 0
page 1
page 2
page 3
page 4
...
0x0000
0x1000
0x2000
0x3000
0x4000
...
0, 1, 2, 3, 0, 1, 4
virtual memory
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