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Lectures
Lecture 04 Annotated
04 - Computer Hardware Review
Outline
Why Review Hardware?
Hardware Model
Processor
Announcements
Reading: MOS 1.3
Hardware Model
The OS is fundamentally tied to hardware.
- Must manage hardware resources for user
- Must provide system calls for interaction
We saw from OS history that the entire purpose
of an OS is to deal directly with hardware so
programmers don't have to.
Simplified model of a PC:
A computer is composed of a CPU, memory, and
I/O devices, all connected by a system bus.
Modern computers are more complicated, but this is
a decent enough model for us.
The Central Processing Unit (CPU) performs all
computations.
CPU context (state) is held in registers.
- General registers for data
- Program counter for next instruction address
- Stack pointer for top stack address
- Status registers for execution information
A register is a small, very fast unit of memory
used to store data during active computation.
CPU may need to switch between executing
multiple different programs.
This is called a context switch.
During a context switch, all the important
registers need to be saved and restored from
kernel memory so programs execute correctly.
Pipelined CPUs can process more than one
instruction in stages for better performance.
Superscalar CPUs improve performance further via
out-of-order execution.
Multithreading/hyperthreading processors
incorporate hardware to support highly performant
context switching.
Multicore processors have multiple independent
CPU cores in a single chip, allowing multiprocessing.
(see MOS Figure 1-8)
There are multiple different types of memory in a
computer used for different purposes.
They are often arranged in a hierarchy organized
by size, performance, and cost.
A cache temporarily holds data fetched from
slower memory in faster memory.
Questions:
Main memory is the addressable memory used by
processes for just about everything.
It is usually volatile (loses data on power loss).
Details out of scope.
Secondary memory is Non-volatile (persistent).
There's lots of types:
Hard Disk Drives are electromechanical, magnetic
storage devices.
I/O devices typically have a hardware controller
with internal registers for configuration.
Depending on the architecture, the processor can
access these registers in one of 2 ways:
I/O operations take a long time.
There are 3 ways to check when they're done:
Interrupts are important enough that they bear
elaboration here.
Interrupt hardware model (Fig 1-11a):
Interrupt software model (Fig 1-11b):
Things to note:
It has been a long time since there has only been
a single system bus in a computer.
Now there are all sorts of buses everywhere, with
many protocols.
> Parallel Bus
> Shared (Bus)
- Each word sent
all at once
- Faster
- Larger footprint
- Devices all connected
to the same wires
- Requires a bridge
controller to manage
- Each word sent
one bit at a time
- Slower
- Smaller footprint
- Devices connected to
CPU separately
- Requires switcher to
manage connections
> Serial Bus
> Point-to-Point (P2P)
Bus architectures:
Many topologies. Here are just 2:
Examples:
PCI (legacy) - parallel, shared
PCIe - serial, P2P
USB - serial, star
SATA - serial, P2P
- Why?
- A single bus limits data throughput
- Kernel is always in memory
- Kernel code is only executed on-demand
via interrupt or system call
- Most CPU time is spent in user-mode programs
The program calls into a device driver which
issues a command to the device controller.
CPU hardware automatically checks for a
pending interrupt if interrupts are enabled.
CPU hardware jumps directly to the kernel-
mode interrupt handler function based on the
provided device id.
The handler saves CPU context, handles the
interrupt, then restores the CPU context and
returns to the interrupted process.
When device controller finishes, it signals the
interrupt controller using dedicated bus lines.
When interrupt controller is ready, it sets a
pin on the CPU to signal a pending interrupt.
The interrupt sets the device id of the
pending interrupt so the CPU can process it.
Most modern architectures now opt for MMIO
Port-mapped I/O (port address space)
Busy-waiting / Polling
Keep checking the device status register.
Have the device send a signal to the processor, which the
processor manages with a context switch.
Special hardware allows devices to directly write to addressable
memory, triggering an interrupt when the transfer is complete.
Interrupts
Direct Memory Access (DMA)
Memory-mapped I/O (shared address space)
- Very cheap, massive storage
- Long-term data reliability
- Rather slow
- Quite fast
- No moving parts
- Data degradation
Floating Gate Transistors
store bits via quantum
tunneling.
Solid State (Flash) Drives are non-volatile
electrical storage devices.
- ROM (Read-only memory)
- EEPROM (Electrically Erasable PROM)
- Hard Disk
- Flash/SSD
Software Interface:
get()
returns hit if data present, miss otherwise
- When to put new items in cache?
- Which cache slot to put the new item in?
- Which item to evict when cache full?
- Where to put evicted items in memory?
stores data in cache
Related: cache coherency
set()
- Hardware cache (e.g. L1, L2, L3)
- managed by hardware, out of scope
- Software cache (e.g. page cache, file cache)
- Fetches instructions from memory,
executes instructions, and updates memory
- Each CPU has an Instruction Set Architecture
(ISA) that defines the machine code format.
ISAs are not portable.
Processor
Memory
I/O Devices
Buses
Make sure to join the Discord!
PA 1 is due Friday.
Start today if you haven't started yet!
1)
2)
3)
4)
5)
Memory
Video
Controller
Keyboard
Controller
USB
Controller
HDD
Controller
MMU
CPU
Bus
I/O Devices
On-board
Based on MOS Figure 1-6
A simplified single-stage RISC-V processor datapath
P&H Figure 4.17
Patterson, D. A., & Hennessy, J. L. (2018). Computer Organization
and Design RISC-V Edition: The Hardware/Software Interface.
Morgan Kaufmann. ISBN: 978-0128122754
Fetch
Unit
Fetch
Unit
Decode
Unit
Decode
Unit
Holding
Buffer
Execute
Unit
Execute
Unit
Execute
Unit
Fetch
Unit
Decode
Unit
Execute
Unit
Simplified 3-stage pipeline from based on MOS Figure 1-7a
Superscalar CPU from MOS Figure 1-7b
Memory
Caches
Main Memory (RAM)
Hard Disk Drive (HDD)
Solid State Drive (SSD/Flash)
I/O Devices
Interrupts
Buses
Additional References
Secondary Memory
Registers
Level
Size
Throughput
Latency
L1 (Cache)
L2 (Cache)
L3 (Cache)
RAM/Main
(Primary)
SSD
(Secondary)
HDD
(Secondary)
~16 kB
~256 GB/s
~250 ps
~1 ns
~3 ns
~10 ns
~100 ns
~200 us
~4 ms
~64 GB/s
~18 GB/s
~5 GB/s
~60 GB/s
~2 GB/s
~500 MB/s
~32 kB
~1 MB
~16-32 MB
~4-64 GB
~256 GB
- 2 TB
~1-18 TB
lower
cost
+
larger
size
higher
perf
Values based on wikipedia:
Memory Hierarchy
DRAM Cell
SRAM Cell
DRAM used for Main Memory
SRAM used for cache
HDD Components
HDD Diagram
HDD Mechanism
SSD Controller
Host Interface
Embedded
Processor
Buffer
Manager
Flash
Controller
Flash
Controller
Flash
Controller
Flash
Memory
Flash
Memory
Flash
Memory
Flash
Memory
Flash
Memory
Flash
Memory
RAM Buffer
Flash Cell
SSD Architecture
1)
1)
2)
2)
3)
MOS Figure 1-11
1)
1)
2)
3)
2)
3)
4)
Intel layout 2007
MOS Figure 1-12
Parallel vs. Serial Interface
PCI vs PCIe Topologies
Some assets from Vecteezy.com
MMU = Memory Management Unit
temporal locality
if you used an address, you are likely to
use it again soon.
if you used an address, you are likely
addresses close by
spacial locality